Chaotic Technique for High Information Security based on Dual-Hiding Asynchronous-Logic AES Accelerator with High Resistance to Prevent Side-Channel Attacks
Author:
Affiliation:
1. Madanapalle Institute of Technology & Science,Dept. of ECE,Andhra Pradesh,India,517 325
2. Sathyabama Institute of Science & Technology,Dept. of CSE,Chennai,India,600 119
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10543256/10543221/10543679.pdf?arnumber=10543679
Reference15 articles.
1. FPGA-Based Hardware Accelerator for Leveled Ring-LWE Fully Homomorphic Encryption
2. Fast Chaotic Image Encryption Algorithm Using a Novel Divide and Conquer Diffusion Strategy
3. Personal Information Two-dimensional Code Encryption Technology in the Process of E-commerce Logistics Transportation
4. A Novel Parallelizable Chaotic Image Encryption Scheme Based on Elliptic Curves
5. Secure and Fast Image Encryption Algorithm Using Hyper-Chaos-Based Key Generator and Vector Operation
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