Design of 5-level reduced switches count Η-bridge multilevel inverter
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/8369063/8371050/08371060.pdf?arnumber=8371060
Cited by 31 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Feasibility study of seven-level two-stage cascaded switch-diode multilevel inverter under different inductive loads;AIP Conference Proceedings;2024
2. A Novel Topology of a Three-Phase Five-Level Reduced Switch Reduced Component Multilevel Inverter;2023 IEEE 3rd International Conference on Smart Technologies for Power, Energy and Control (STPEC);2023-12-10
3. An Asymmetrical Active-Neutral-Point-Clamped Five-Level H-bridge Inverter for Open-Winding Motor Applications With Its Modulation Strategy;IEEE Transactions on Power Electronics;2023-10
4. Design, Analysis & Performance Improvement of A Modified Asymmetrical H-Bridge Multilevel Inverter By Metaheuristic Algorithms;2023 IEEE 3rd International Conference on Sustainable Energy and Future Electric Transportation (SEFET);2023-08-09
5. Analysis and Mitigation of Low-Order-Harmonic Neutral-Point Voltage and Current Ripples in Five-Level NPC-Based Inverters;2023 IEEE 32nd International Symposium on Industrial Electronics (ISIE);2023-06-19
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