Design of Power Delay Efficient Wallace Muliplier
Author:
Affiliation:
1. Dr. Mahalingam College of Engineering and Technology,Department of ECE,Coimbatore,India
2. Sri Eshwar College of Engineering,Department of ECE,Coimbatore,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10112659/10112660/10112916.pdf?arnumber=10112916
Reference18 articles.
1. Design of 4-bit Carry look ahead Adder using self resetting and gate diffusion input logics;dhanasekar;Solid Sate Technol,2020
2. Multipliers With Approximate 4–2 Compressors and Error Recovery Modules
3. A Survey of Various Higher Order Majority Gates Utilized in Novel Quantum Dot Cellular Automata Technology (QCA);ishwarya niranjana;International Conference on Augmented Intelligence and Sustainable Systems (ICAISS),2022
4. Improved Modified Area Efficient Carry Select Adder (MAE-CSLA) Without Multiplexer
5. Approximate Computing: A Survey
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