Truncated Booth Multiplier Design Of Approximate Compressors Using Verilog Hdl

Author:

N Senthilkumar1,Pon Elanchandhar1,K Bharanidharan1,Kumar M Akash1

Affiliation:

1. M.Kumarasamy College of Engineering,Department of ECE,Karur,India

Publisher

IEEE

Reference18 articles.

1. Low-Power Digital Signal Processing Using Approximate Adders

2. 14.3 A 28 nm SoC with a 1.2 GHz 568 nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications;whatmough;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2017

3. Log-determinant relaxation for approximate inference in discrete Markov random fields

4. An Approximate and Efficient Method for Optimal Rotation Alignment of 3D Models

5. Approximate Floating-Point Multiplier based on Static Segmentation;traiola;Electronics,2022

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