Compact Modeling of Surface Potential, Charge, and Current in Nanoscale Transistors Under Quasi-Ballistic Regime

Author:

Dasgupta AvirupORCID,Agarwal Amit,Khandelwal Sourabh,Chauhan Yogesh Singh

Funder

Ramanujan fellowship research grant

Council of Scientific and Industrial Research, India

Science and Engineering Research Board, India

Semiconductor Research Corporation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Physics-Based Compact Model for Silicon Cold-Source Transistors;IEEE Transactions on Electron Devices;2023-04

2. An optimized nanoscale Quasi-Ballistic DG MOSFET model with diffusive carrier scattering dependency;International Journal of Electronics;2022-05-05

3. Proposal of Ferroelectric Based Electrostatic Doping for Nanoscale Devices;IEEE Electron Device Letters;2021-04

4. Analytical model for quasi-ballistic transport in MOSFET including carrier backscattering;Journal of Computational Electronics;2021-02-24

5. Compact Modeling of Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport;2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2020-04

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