A network processor architecture for flexible QoS control in very high-speed line interfaces-Reference-Cited by-同舟云学术

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A network processor architecture for flexible QoS control in very high-speed line interfaces

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Container-title:2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552)
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Author:

Shimonishi H.,Murase T.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/7362/19970/00923669.pdf?arnumber=923669

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and implementation of a random neural network routing engine;IEEE Transactions on Neural Networks;2003-09

2. Fundamental architectural considerations for network processors;Computer Networks;2003-04

3. On-Chit High-Speed Solver of Inverse Problems Based on Quantum-Computing Principle;2006 IEEE International Symposium on Circuits and Systems

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