Graph Theory Approach for Multi-site ATE Board Parameter Extraction
Author:
Affiliation:
1. Iowa State University,Ames,IA,USA
2. Texas Instruments,Dallas,TX,USA
3. Texas Instruments,Houston,TX,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9810327/9810358/09810391.pdf?arnumber=9810391
Reference6 articles.
1. Reducing integrated circuit test cost through improvements in multisite testing and built-in self-test;al-obaidi;Grad Theses Diss,2020
2. Site dependencies in a multisite testing environment
3. Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
4. Quantile – Quantile Fitting Approach to Detect Site to Site Variations in Massive Multi-site Testing
5. Test cost saving and challenges in the implementation of /spl times/6 and /spl times/8 parallel testing on freescale 16-bit HCS12 microcontroller product family
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1. Design and Implementation of Test System for System Chip Function Test;2023 3rd International Conference on Electronic Information Engineering and Computer Communication (EIECC);2023-12-22
2. Cross-Correlation Approach to Detecting Issue Test Sites in Massive Parallel Testing;2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2022-10-19
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