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Multiple-Valued Logic Charge-Coupled Devices

Published:1981-09 Issue:9 Volume:C-30 Page:644-652
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Kerkhoff ,Tervoert

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx5/12/35207/01675862.pdf?arnumber=1675862

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low Power Scalable Ternary Hybrid Full Adder Realization;2020 32nd International Conference on Microelectronics (ICM);2020-12-14

2. Memristor-CNTFET based ternary logic gates;Microelectronics Journal;2018-02

3. Universal Set of CMOS Gates for the Synthesis of Multiple Valued Logic Digital Circuits;IEEE Transactions on Circuits and Systems I: Regular Papers;2014-03

4. Four Decades of Multi-Valued Logic: Lists of Highly Cited Papers;2013 IEEE 43rd International Symposium on Multiple-Valued Logic;2013-05

5. All-optical quaternary computing and information processing: a promising path;Journal of Optics;2013-03-17

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