Design of Easily Testable Bit-Sliced Systems-Reference-Cited by-同舟云学术

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Design of Easily Testable Bit-Sliced Systems

Published:1981-11 Issue:11 Volume:C-30 Page:842-854
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Sridhar ,Hayes

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx5/12/35199/01675715.pdf?arnumber=1675715

Cited by 44 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Combined pseudo-exhaustive and deterministic testing of array multipliers;2018 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR);2018-05

2. Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells;2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS);2018-04

3. Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018

4. Design-for-testability techniques for CORDIC design;Microelectronics Journal;2009-10

5. Scalable and bijective cells for C-testable iterative logic array architectures;IET Circuits, Devices & Systems;2009-08-01

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