A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication-Reference-Cited by-同舟云学术

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A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication

Published:2023-10-16 Issue: Volume: Page:
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Container-title:2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)
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Author:

Eggermann Grégoire¹,Rios Marco¹,Ansaloni Giovanni¹,Nassif Sani²,Atienza David¹

Affiliation:

1. École Polytechnique fédérale de Lausanne (EPFL),Embedded Systems Laboratory (ESL),Switzerland

2. Radyalis,Austin,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10321814/10321836/10321838.pdf?arnumber=10321838

Reference18 articles.

1. Matrix computations (Johns Hopkins studies in mathematical sciences);l;Matrix Computations,1996

2. A Graph-to-Sequence Model for AMR-to-Text Generation

3. Generalized Nested Dissection

4. Improving performance of sparse matrix-vector multiplication

5. Hybrid approach of relation network and localized graph convolutional filtering for breast cancer subtype classification;rhee,2017

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Hardware Instruction Generation Mechanism for Energy-Efficient Computational Memories;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

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