Clock Period Minimization with Minimum Delay Insertion

Author:

Huang Shih-Hsu,Cheng Chun-Hua,Chang Chia-Ming,Nieh Yow-Tyng

Publisher

IEEE

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Synchronization in VLSI;Graphs in VLSI;2022-06-30

2. Power-aware hold optimization for ASIC physical synthesis;Integration;2021-01

3. Multi-Objective Robust Optimization of a Dual-Flux-Modulator Magnetic Geared Machine With Hybrid Uncertainties;IEEE Transactions on Energy Conversion;2020-12

4. Power and Area Efficient Hold Time Fixing by Free Metal Segment Allocation;Proceedings of the 54th Annual Design Automation Conference 2017;2017-06-18

5. A Compact Low Power High Frequency Pulse Generator;2015 Fifth International Conference on Communication Systems and Network Technologies;2015-04

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