Author:
Aksoy Levent,Costa Eduardo,Flores Paulo,Monteiro Jose
Cited by
17 articles.
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1. Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-01
2. Design of Optimal Multiplierless FIR Filters With Minimal Number of Adders;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-02
3. Truncated Multiple Constant Multiplication with Minimal Number of Full Adders;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
4. Application-Specific Arithmetic in High-Level Synthesis Tools;ACM Transactions on Architecture and Code Optimization;2020-03-31
5. Table-Based versus Shift-And-Add Constant Multipliers for FPGAs;2019 IEEE 26th Symposium on Computer Arithmetic (ARITH);2019-06