Author:
Srivastava Shweta,Roychowdhury Jaijeet
Cited by
11 articles.
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1. An Efficient Timing Model of Flip-Flops Based on Artificial Neural Network;2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD);2021-08-30
2. EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-04
3. Circuit Timing Analysis and Optimization under Flexible Flip-flop Timing Model;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2017-12-31
4. PieceTimer;Proceedings of the 35th International Conference on Computer-Aided Design;2016-11-07
5. Post-Silicon Tuning Based on Flexible Flip-Flop Timing;JSTS:Journal of Semiconductor Technology and Science;2016-02-28