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Efficient Jitter Analysis for a Chain of CMOS Inverters

  • Published:2020-02 Issue:1 Volume:62 Page:229-239
  • ISSN:0018-9375
  • Container-title:IEEE Transactions on Electromagnetic Compatibility
  • language:
  • Short-container-title:IEEE Trans. Electromagn. Compat.

Author:

Tripathi Jai NarayanORCID,Arora Puneet,Shrimali Hitesh,Achar RamachandraORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Atomic and Molecular Physics, and Optics

Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Multiobjective Optimization for PSIJ Mitigation and Impedance Improvement Based on PCPS/DR-NSDE in Chiplet-Based 2.5-D Systems;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08

2. Prediction of Power Supply Induced Jitter via Deep Belief and Knowledge-Based Neural Networks;2024 IEEE 28th Workshop on Signal and Power Integrity (SPI);2024-05-12

3. Ultrawideband Power-Noise Suppression Based on Lossy Capacitors With Low-Frequency Stopband Enhancement for Digital Systems;IEEE Transactions on Signal and Power Integrity;2024

4. Modeling Power Supply and Ground-Bounce Induced Jitter for a Voltage-Mode Driver Circuit driving Long Transmission Lines;2023 IEEE Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMC+SIPI);2023-07-29

5. Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-06
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