Design-for-Security vs. Design-for-Testability: A Case Study on DFT Chain in Cryptographic Circuits

Author:

Jin Yier

Publisher

IEEE

Cited by 25 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Trojan Localization Using Information Flow Tracking Properties in SoC Designs;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

2. Hardware/software security co-verification and vulnerability detection: An information flow perspective;Integration;2024-01

3. SpecCheck: A Tool for Systematic Identification of Vulnerable Transient Execution in gem5;2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT);2023-10-21

4. Timestamp-Based Secure Shield Architecture for Detecting Invasive Attacks;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-09

5. A Review of Intelligent Design for Test Based on Machine Learning;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08

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