Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit-Reference-Cited by-同舟云学术

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Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit

Published:2012-08 Issue: Volume: Page:
ISSN:
Container-title:2012 IEEE Computer Society Annual Symposium on VLSI
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Author:

Arnold Oliver,Noethen Benedikt,Fettweis Gerhard

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6296433/6296435/06296481.pdf?arnumber=6296481

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. FPGA implementation of hardware accelerated RTOS based on real-time event handling;The Journal of Supercomputing;2023-03-13

2. A Hierarchical Task Scheduler for Heterogeneous Computing;Lecture Notes in Computer Science;2021

3. Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies;IEEE Access;2020

4. A Task-Level Monitoring Framework for Multi-Processor Platforms;Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems;2016-05-23

5. Tomahawk;ACM Transactions on Embedded Computing Systems;2014-03

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