An Automated Hardware/Software Co-Design Flow for Partially Reconfigurable FPGAs
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/7558446/7560148/07560168.pdf?arnumber=7560168
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources;ACM Transactions on Design Automation of Electronic Systems;2023-10-28
2. Architecture Design of Reconfigurable Sensing Terminal Platform Considering Distributed Energy;2023 IEEE/IAS Industrial and Commercial Power System Asia (I&CPS Asia);2023-07-07
3. Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC;Proceedings of the 36th Annual ACM Symposium on Applied Computing;2021-03-22
4. Incremental Learning for Real-time Partitioning for FPGA Applications;Proceedings of the 13th International Conference on Agents and Artificial Intelligence;2021
5. The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW;Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies - HEART 2019;2019
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