Artificial Neural Network Surrogate Models for Efficient Design Space Exploration of 14-nm FinFETs
Author:
Affiliation:
1. Indian Institute of Technology,Roorkee,Uttarakhand,India,247667
2. Indian Institute of Technology Roorkee, Uttarakhand 247667, India
3. University of California,Berkeley,CA,USA,94720
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9855770/9855647/09855816.pdf?arnumber=9855816
Reference5 articles.
1. Artificial neural network design for compact modeling of generic transistors
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