Timing and area optimization for standard-cell VLSI circuit design-Reference-Cited by-同舟云学术

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Timing and area optimization for standard-cell VLSI circuit design

Published:1995-03 Issue:3 Volume:14 Page:308-320
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Weitong Chuang ,Sapatnekar S.S.,Hajj I.N.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx1/43/8364/00365122.pdf?arnumber=365122

Cited by 20 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence;2021 IEEE International Symposium on Circuits and Systems (ISCAS);2021-05

3. Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence;2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID);2021-02

4. Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach;Proceedings of the 2019 International Symposium on Physical Design;2019-04-04

5. Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices;2014 IEEE Computer Society Annual Symposium on VLSI;2014-07

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