An Efficient and Robust Modified Hybrid Multipliers with Less Power and Better Speed

Author:

Gomathi V.1,Varshan M.Shree1,Subramaniyan V.1,Krishna S.Udaya1

Affiliation:

1. Saveetha Engineering College,Department of ECE,Chennai,India

Publisher

IEEE

Reference15 articles.

1. An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic;mohan;Electronics,2017

2. High speed and area-efficient multiply accumulate (MAC) unit for digital signal prossing applications Circuits and Systems, ISCAS 2007;abdelgawad;IEEE International Symposium on,2007

3. Efficient modular hybrid adders and Radix-4 booth multipliers for DSP applications;pramod;Microelectronics Journal DOI 10 1016/j mejo 2020 104701,2020

4. Faster and Energy-Efficient Signed Multipliers

5. An architecture for 32-bit energy-efficient wallace tree carry save adder

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