A gigabit MOS logic circuit with buried channel MOSFETs-Reference-Cited by-同舟云学术

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A gigabit MOS logic circuit with buried channel MOSFETs

Published:1980-10 Issue:5 Volume:15 Page:809-816
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Nishiuchi K.,Shibayama H.,Nakamura T.,Hisatsugu T.,Ishikawa H.,Fukukawa Y.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/22573/01051475.pdf?arnumber=1051475

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Potential-Based Modeling of Depletion-Mode MOSFET Applicable for Structural Variations;IEEE Transactions on Electron Devices;2019-01

2. Potential and electron distribution model for the buried-channel MOSFET;IEEE Transactions on Electron Devices;1989-04

3. Simulation of the accumulation-punchthrough mode in depletion MOSFETs;Solid-State Electronics;1986-10

4. Electron lithography for the fabrication of microelectronic devices;Reports on Progress in Physics;1985-06-01

5. Nanometer-scale silicon mosfets;Microelectronic Engineering;1984-10

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