A defect-tolerant design for full-wafer memory LSI-Reference-Cited by-同舟云学术

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A defect-tolerant design for full-wafer memory LSI

Published:1984-06 Issue:3 Volume:19 Page:319-324
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Ueoka Y.,Minagawa C.,Oka M.,Ishimoto A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/22596/01052144.pdf?arnumber=1052144

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Efficient Algorithm for Spare Allocation Problems;IEEE Transactions on Reliability;2006-06

2. A study of network logic for wafer-scale parallel-access memory and a yield analysis;Systems and Computers in Japan;1995

3. Tolerating faults in a mesh with a row of spare nodes;Theoretical Computer Science;1994-06

4. Restructuring of square processor arrays by built-in self-repair circuit;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;1993

5. Defect- and fault-tolerant static ram module designs based on parity checking and automatic testing;Systems and Computers in Japan;1993

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