VLSI and AES based IoT security by Modified Random S- Box Generation-Reference-Cited by-同舟云学术

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VLSI and AES based IoT security by Modified Random S- Box Generation

Published:2022-11-26 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON)
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Author:

Das Indrajit¹,Jha Kashmira²,Debnath Papiya³,Nath Subhrapratim²

Affiliation:

1. Meghnad Saha Institute of Technology,Dept. of Information Technology,Kolkata,India

2. Meghnad Saha Institute of Technology,Dept. of Computer Science & Engineering,Kolkata,India

3. Techno International New Town,Dept. of Basic Science and Humanities (Mathematics),Kolkata,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10032824/10032825/10032902.pdf?arnumber=10032902

Reference12 articles.

1. Analysis of NAND/NOR gates using subthreshold adiabatic logic (SAL) for ultra low power applications

2. Analysis of Sub-Threshold Adiabatic Logic Model Using Junctionless MOSFET for Low Power Application;roy;Silicon,2022

3. AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications

4. VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

5. Arrhythmic Heartbeat Classification Using Ensemble of Random Forest and Support Vector Machine Algorithm

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