Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits-Reference-Cited by-同舟云学术

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Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits

Published:2019-04 Issue:4 Volume:66 Page:1648-1655
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Chen Chun-Cheng^ORCID,Ker Ming-Dou^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/8668593/08645796.pdf?arnumber=8645796

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Influence of Temperature on the EFT Immunity of Multistage Integrated Oscillators;IEEE Transactions on Electromagnetic Compatibility;2023-02

2. Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter;Electronics;2023-01-20

3. Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions;IEEE Journal of the Electron Devices Society;2023

4. Latch-Up Prevention With Autodetector Circuit to Stop Latch-Up Occurrence in CMOS-Integrated Circuits;IEEE Transactions on Electromagnetic Compatibility;2022-12

5. Robust HV Power pLDMOS Components for ESD Protection by the Drain-side Parasitic Schottky Diode and SCR Engineering;2022 International Power Electronics Conference (IPEC-Himeji 2022- ECCE Asia);2022-05-15

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