A highly latchup-immune 1-µm CMOS technology fabricated with 1-MeV ion implantation and self-aligned TiSi2-Reference-Cited by-同舟云学术

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A highly latchup-immune 1-µm CMOS technology fabricated with 1-MeV ion implantation and self-aligned TiSi2

Published:1986-09 Issue:9 Volume:33 Page:1308-1320
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Fang-Shi J. Lai ,Wang L.K.,Yuan Taur ,Sun J.Y.-C.,Petrillo K.E.,Chicotka S.K.,Petrillo E.J.,Polcari M.R.,Bucelot T.J.,Zicherman D.S.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/16/31956/01485881.pdf?arnumber=1485881

Cited by 22 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Comparison of latchup immunity for silicided source/drain at different n+ implant energy;Microelectronics Reliability;1998-09

2. Comparison of retrograde and conventional p-wells in regard of latch-up susceptibility;Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms;1995-03

3. CMOS scaling into the 21st century: 0.1 µm and beyond;IBM Journal of Research and Development;1995-01

4. Dramatic increases in latchup holding voltage for sub-0.5 /spl mu/m CMOS using shallow S/D junctions;IEEE Electron Device Letters;1994-11

5. Improved device performance by multistep or carbon co-implants;IEEE Transactions on Electron Devices;1994

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