Design and Performance Analysis of FPGA based DPU using MAC Unit-Reference-Cited by-同舟云学术

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Design and Performance Analysis of FPGA based DPU using MAC Unit

Published:2023-04-07 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE 8th International Conference for Convergence in Technology (I2CT)
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Author:

Mule Priya C¹,Mande Sudhakar²

Affiliation:

1. Ramrao Adik Institute of Technology,Electronics and Telecommunication,Navi Mumbai,India

2. Don Bosco Institute of Technology,Electronics and Telecommunication,Mumbai,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10126131/10126116/10126363.pdf?arnumber=10126363

Reference10 articles.

1. High Performance MAC Unit for FFT Implementation;tresa;International Journalof Modern Engineering and Research,2014

2. Design of Systolic Array Architecture for Matrix Multiplication Inference on FPGA;singh;International Journal for Scientific Research and Development,2018

3. Multiplier – Accumulator (MAC) unit;nain;International Journal of Digital Application and Contemporary Research,2016

4. Simulation Result Analysis of Efficient Design of Systolic Architecture;p;International Journal of Engineering Research and Technology(IJERT),2018

5. Design and Implementation Of Sytolic Array Architecture;singh;Journal of Electrical and Electronics Engineering Research,2013

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