Author:
Yoshikawa Senri,Sannomiya Shuji,Iwata Makoto,Nishikawa Hiroaki
Cited by
4 articles.
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1. Self-Timed Counter Synthesis;2024 International Conference on Industrial Engineering, Applications and Manufacturing (ICIEAM);2024-05-20
2. Self-Timed Pipeline with Variable Stage Number*;2023 Seminar on Networks, Circuits and Systems (NCS);2023-11-29
3. Automated Mapping of Asynchronous Circuits on FPGA under Timing Constraints;2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2022-07
4. Automatic golden device selection and measurement smoothing algorithms for microwave transistor small-signal noise modeling;International Journal of Microwave and Wireless Technologies;2022-06-16