A 1.75 mW 1.1 GHz Semi-Digital Fractional-N PLL With TDC-Less Hybrid Loop Control-Reference-Cited by-同舟云学术

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A 1.75 mW 1.1 GHz Semi-Digital Fractional-N PLL With TDC-Less Hybrid Loop Control

Published:2012-12 Issue:12 Volume:22 Page:654-656
ISSN:1531-1309
Container-title:IEEE Microwave and Wireless Components Letters
language:
Short-container-title:IEEE Microw. Wireless Compon. Lett.

Author:

Sun Yuanfeng,Zhang Zhuo,Xu Ni,Wang Min,Rhee Woogeun,Oh Tae-Young,Wang Zhihua

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics

Link

http://xplorestaging.ieee.org/ielx5/7260/6374739/06365279.pdf?arnumber=6365279

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Digital‐Intensive PLL;Phase‐Locked Loops;2023-12-22

2. A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and −251.6 dB FoM;Sensors;2021-11-18

3. Analysis and Modeling of Hybrid Analog-digital PLL;2021 IEEE 15th International Conference on Electronic Measurement & Instruments (ICEMI);2021-10-29

4. A Bias-Current-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-09

5. CMOS analog and mixed-signal phase-locked loops: An overview;Journal of Semiconductors;2020-11-01

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