Author:
Pavlovic Vladimir,Stanisavljevic Zarko,Nikolic Bosko,Dordevic Jovan
Cited by
2 articles.
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1. Verilog HDL Simulator Technology: A Survey;Journal of Electronic Testing;2014-05-23
2. A Module for Automatic Assessment and Verification of Students' Work in Digital Logic Design;2012 IEEE 19th International Conference and Workshops on Engineering of Computer-Based Systems;2012-04