Design of Compact Vedic Multiplier for High Performance Circuits-Reference-Cited by-同舟云学术

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Design of Compact Vedic Multiplier for High Performance Circuits

Published:2018-05 Issue: Volume: Page:
ISSN:
Container-title:2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)
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Author:

Pooja V. G.,Premananda B. S.,Ramesh Gouthaami S.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8977133/9012088/09012654.pdf?arnumber=9012654

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Systematic exploration of N-bit Vedic multipliers: A roadmap of technological approaches in pursuit of future trends;Nano Communication Networks;2024-12

2. QCA Implementation of Arithmetic Unit using Reversible Logic Gates;2024 7th International Conference on Devices, Circuits and Systems (ICDCS);2024-04-23

3. A more generalized algorithm of Vedic sutra: Urdhva-Tiryagbhyam for 2n-bit square calculation using Quantum-dots;2023 Second International Conference on Advances in Computational Intelligence and Communication (ICACIC);2023-12-07

4. Design and Simulation of a Novel Cell Interaction Based Square Calculator in Quantum-Dot Cellular Automata;2023 International Conference on Wireless Communications Signal Processing and Networking (WiSPNET);2023-03-29

5. Delay-Efficient Vedic Multiplier Design Using 4:3 Counter for Complex Multiplication;Lecture Notes in Electrical Engineering;2023

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