A Digitally-Calibrated 70.98dB-SNDR 625kHz-Bandwidth Temperature-Tolerant 2nd-order Noise-Shaping SAR ADC in 65nm CMOS
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/9043348/9056889/09056963.pdf?arnumber=9056963
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 73-dB-SNDR 2nd-Order Noise-Shaping SAR With a Low-Noise Time-Domain Comparator;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-08
2. Open-source design of integrated circuits;e+i Elektrotechnik und Informationstechnik;2024-01-09
3. A 12-ENOB Second-Order Noise-Shaping SAR ADC With PVT-Insensitive Voltage– Time–Voltage Converter;IEEE Journal of Solid-State Circuits;2023-10
4. A Review of Noise Reduction Techniques in Noise-shaping SAR ADCs;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2022-12-31
5. A 2.5-MHz BW, 75-dB SNDR Noise-Shaping SAR ADC With a 1st-Order Hybrid EF-CIFF Structure Assisted by Unity-Gain Buffer;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-12
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