A Noble Design Methodology to Minimize Plasma Induced Damage Using a Distributed Network Model in VNAND Flash Memory-Reference-Cited by-同舟云学术

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A Noble Design Methodology to Minimize Plasma Induced Damage Using a Distributed Network Model in VNAND Flash Memory

Published:2023-12-09 Issue: Volume: Page:1-4
ISSN:
Container-title:2023 International Electron Devices Meeting (IEDM)
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Author:

Lee Se Hoon¹,Um Junghwan²,Kim Kanglib¹,Lee Kyoungseo¹,Chang Seongpil¹,Lee Jaeshin¹,Han Hunhee¹,Cho Sungil²,Lim Junhee¹,Park Minchul¹,Hur Sunghoi³

Affiliation:

1. Memory Business Samsung Electronics Co.,Flash Process Architecture Team 2,Hwaseong-si,Korea

2. Global Manufacturing & Infra Technology Samsung Electronics Co.,Memory Etch Technology Team,Hwaseong-si,Korea

3. Memory Business Samsung Electronics Co.,Flash Product and Technology,Hwaseong-si,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10413659/10413660/10413668.pdf?arnumber=10413668

Reference11 articles.

1. Impact of plasma charging damage and diode protection on scaled thin oxide

2. New interconnect plasma induced damage analyzed by flash memory cell array

3. Yield and reliability effects of interlevel dielectric plasma enhanced deposition induced charging damage

4. Plasma charging damage during contact hole etch in high-density plasma etcher

5. Highly manufacturable 7th generation 3D NAND flash memory with COP structure and double stack process;Kim

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