Author:
Capocelli R.M.,Giancarlo R.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Cited by
36 articles.
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1. A Generalized Residue Number System Design Approach for Ultralow-Power Arithmetic Circuits Based on Deterministic Bit-Streams;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11
2. Efficient Implementation of Modular Division by Input Bit Splitting;2019 IEEE 26th Symposium on Computer Arithmetic (ARITH);2019-06
3. RNS-Based Arithmetic Circuits and Applications;Arithmetic Circuits for DSP Applications;2017-09-08
4. Optimizing Residue Number System on FPGA;2016 IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, Physical and Social Computing (CPSCom) and IEEE Smart Data (SmartData);2016-12
5. Binary to RNS encoder for the moduli set {2n-1, 2n, 2n+1} with embedded diminished-1 channel for DSP application;Facta universitatis - series: Electronics and Energetics;2016