A trace-driven simulator for performance evaluation of cache-based multiprocessor systems-Reference-Cited by-同舟云学术

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A trace-driven simulator for performance evaluation of cache-based multiprocessor systems

Published:1995 Issue:9 Volume:6 Page:915-929
ISSN:1045-9219
Container-title:IEEE Transactions on Parallel and Distributed Systems
language:
Short-container-title:IEEE Trans. Parallel Distrib. Syst.

Author:

Prete C.A.,Prina G.,Ricciardi L.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Signal Processing

Link

http://xplorestaging.ieee.org/ielx4/71/9787/00466630.pdf?arnumber=466630

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Using the first-level cache stack distance histograms to predict multi-level LRU cache misses;Microprocessors and Microsystems;2017-11

2. A Very Fast Trace-Driven Simulation Platform for Chip-Multiprocessors Architectural Explorations;IEEE Transactions on Parallel and Distributed Systems;2017-11-01

3. Efficient Generation of Compact Execution Traces for Multicore Architectural Simulations;ACM Transactions on Architecture and Code Optimization;2017-09-06

4. Mesoscale performance simulation of multicore processor systems;Software & Systems Modeling;2012-01-29

5. A Model-Based Method for Evaluating Embedded System Performance by Abstraction of Execution Traces;Modelling Foundations and Applications;2010

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