Design and Analysis of a Low-Power Two-Stage Dynamic Comparator with 40ps Delay in 65nm CMOS Technology-Reference-Cited by-同舟云学术

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Design and Analysis of a Low-Power Two-Stage Dynamic Comparator with 40ps Delay in 65nm CMOS Technology

Published:2021-05-18 Issue: Volume: Page:
ISSN:
Container-title:2021 29th Iranian Conference on Electrical Engineering (ICEE)
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Author:

Ghasemi Razieh,Ghasemian Hossein,Abiri Ebrahim,Salehi Mohammad Reza

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9544084/9543706/09544241.pdf?arnumber=9544241

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Two-stage Dynamic Comparator with Low Delay and Low Offset;2023 3rd International Conference on Intelligent Power and Systems (ICIPS);2023-10-20

2. 45nm CMOS Two-Stage Latched Comparator;2022 International Conference on Smart Systems and Power Management (IC2SPM);2022-11-10

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