Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC
Author:
Affiliation:
1. Department of Quantum & Computing Engineering & QuTech,TU Delft,The Netherlands
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9911257/9911222/09911474.pdf?arnumber=9911474
Reference10 articles.
1. High-frequency noise in nanoscale metal oxide semiconductor field effect transistors
2. Noise Analysis for Comparator-Based Circuits
3. Characterization of Shot Noise Suppression in Nanometer MOSFETs
4. 13.4 A 1GS/s 6-to-8b 0.5mW/Qubit Cryo-CMOS SAR ADC for Quantum Computing in 40nm CMOS
5. A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits
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1. A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS;IEEE Journal of Solid-State Circuits;2024-07
2. A 7-10b Programmable Cryo-CMOS TI-SAR ADC for Multichannel Qubit Readout with On-Chip Background Inter-Channel Mismatch Calibrations;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11
3. A Benchmark of Cryo-CMOS 40-nm Embedded SRAM/DRAMs for Quantum Computing;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11
4. Cryo-CMOS Mixed-Signal Circuits for Scalable Quantum Computing: Challenges and Future Steps;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
5. A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing;IEEE Transactions on Circuits and Systems I: Regular Papers;2023
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