COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits

Author:

Reddy ,Pomeranz ,Reddy

Publisher

IEEE Comput. Soc. Press

Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Sharing of Topped-Off Compressed Test Sets Among Logic Blocks;IEEE Access;2024

2. Topping Off Test Sets Under Bounded Transparent Scan;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-01

3. Two-Dimensional Test Generation Objective;2022 IEEE 31st Asian Test Symposium (ATS);2022-11

4. Transforming an $n$-Detection Test Set into a Test Set for a Variety of Fault Models;2022 IEEE International Test Conference (ITC);2022-09

5. Increasing the Fault Coverage of a Truncated Test Set;ACM Transactions on Design Automation of Electronic Systems;2022-06-27

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