Author:
Ghiasi S.,Bozorgzadeh E.,Choudhuri S.,Sarrafzadeh M.
Cited by
21 articles.
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1. Timing Closure;VLSI Physical Design: From Graph Partitioning to Timing Closure;2022
2. Process variation-aware gate sizing with fuzzy geometric programming;Computers & Electrical Engineering;2019-09
3. Quality-Time Tradeoffs in Component-Specific Mapping;Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2017-02-22
4. Discretized Network Flow Techniques for Timing and Wire-Length Driven Incremental Placement With White-Space Satisfaction;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2011-07
5. On Incremental Component Implementation Selection in System Synthesis;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2010-11