System level design and verification using a synchronous language-Reference-Cited by-同舟云学术

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System level design and verification using a synchronous language

Published:2003 Issue: Volume: Page:
ISSN:
Container-title:ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)
language:
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Author:

Berry G.,Kishinevsky M.,Singh S.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/8895/28127/01257813.pdf?arnumber=1257813

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A methodology to take credit for high-level verification during RTL verification;Formal Methods in System Design;2017-09-19

2. Formally Unifying Modeling and Design for Embedded Systems - A Personal View;Leveraging Applications of Formal Methods, Verification and Validation: Discussion, Dissemination, Applications;2016

3. Towards Safe Design of Synchronous Bus Protocols in Event-B;Lecture Notes in Computer Science;2009

4. Formal Verification of Gate-Level Computer Systems;Computer Science - Theory and Applications;2009

5. A new tool-kit for designing complex material handling systems using IEC61499 function blocks;IFAC Proceedings Volumes;2009

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