Generating FPGA-based image processing accelerators with Hipacc: (Invited paper)
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8167715/8203744/08203894.pdf?arnumber=8203894
Cited by 26 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Allo: A Programming Model for Composable Accelerator Design;Proceedings of the ACM on Programming Languages;2024-06-20
2. SlidingConv: Domain-Specific Description of Sliding Discrete Cosine Transform Convolution for Halide;IEEE Access;2024
3. FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler;ACM Transactions on Architecture and Code Optimization;2023-12-14
4. An Analysis of Accelerator Data-Transfer Modes in NoC-Based SoC Architectures;2023 IEEE High Performance Extreme Computing Conference (HPEC);2023-09-25
5. Sparse-HeteroCL: From Sparse Tensor Algebra to Highly Customized Accelerators on FPGAs;2023 IEEE/ACM 23rd International Symposium on Cluster, Cloud and Internet Computing Workshops (CCGridW);2023-05
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