Author:
Hu Jin,Schaeffer Greg,Garg Vibhor
Cited by
6 articles.
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1. Accelerating Static Timing Analysis Using CPU–GPU Heterogeneous Parallelism;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-12
2. A GPU-Accelerated Framework for Path-Based Timing Analysis;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11
3. General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09
4. DAC-CPPR: A fast and accurate approach for common path pessimism removal with divide and conquer on the clock tree;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08
5. Efficient Critical Paths Search Algorithm using Mergeable Heap;2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC);2022-01-17