Author:
Chuang Yi-Lin,Nam Gi-Joon,Alpert Charles J.,Chang Yao-Wen,Roy Jarrod,Viswanathan Natarajan
Cited by
13 articles.
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1. A Routability-Driven Ultrascale FPGA Macro Placer with Complex Design Constraints;2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2024-05-05
2. Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-Scale Complex IP Blocks;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023
3. RTL-MP;Proceedings of the 2022 International Symposium on Physical Design;2022-04-13
4. Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical Methods;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021-12
5. DAPA: A Dataflow-Aware Analytical Placement Algorithm for Modern Mixed-Size Circuit Designs;2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD);2021-11-01