Performance Analysis of RNS Arithmetic Operations using Reversible Logic
Author:
Affiliation:
1. JSS Academy of Technical Education,Department of ECE,Bengaluru,India
2. School of Electronics and Communication, KLE Technological University,Hubballi,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10059463/10059582/10060538.pdf?arnumber=10060538
Reference15 articles.
1. Analysis and Design of High Speed Residue to Binary Reverse Converter for the Moduli Set {2n+ 1, 2n,2n-1}
2. Architecture of efficient RNS-based digital signal processor with very low-level pipelining
3. An Algorithm for Magnitude Comparison in RNS based on Mixed-Radix Conversion II
4. Fast division in the residue number system {2 + 1,2 , 2 -1} based on shortcut mixed radix conversion
5. General modular adder designs for residue number system applications
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