A Design of High Resolution ADC-Assisted Gated-Ring Oscillator TDC with Digital Calibration
Author:
Affiliation:
1. SKAIChips,Suwon,South Korea
2. Sungkyunkwan University,Department of Electrical and Computer Engineering,Suwon,South Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10391854/10391860/10392380.pdf?arnumber=10392380
Reference4 articles.
1. A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping
2. An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator TDC
3. A 2.8–3.2-GHz Fractional-$N$ Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO
4. A 14-nm 0.14-psrmsFractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration
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