Attacking a Joint Protection Scheme for Deep Neural Network Hardware Accelerators and Models
Author:
Affiliation:
1. University of Ulm,Institute of Microelectronics,Ulm,Germany
2. University of Stuttgart,Institute for Computer Architecture and Computer Engingeering,Stuttgart,Germany
Funder
National Science Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10595550/10595552/10595935.pdf?arnumber=10595935
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3. A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations;Fujiwara
4. DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge
5. 22.1 A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing
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