10GB MAC CORE Verification - Scoreboard Module
Author:
Affiliation:
1. Kalasalingam Academy of Research and Education,Department of Electronics and Communication Engineering,Krishnankoil,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10156871/10156874/10157471.pdf?arnumber=10157471
Reference14 articles.
1. Design and verification of a layer-2 Ethernet MAC classification engine for a Gigabit Ethernet switch;tonfat;2010 17th IEEE International Conference on Electronics, Circuits and Systems,2011
2. Reusable Verification Environment for verification of Ethernet packet in Ethernet IP core, a verification strategy- an analysis;jyothi;International Journal of Computer Science and Network Security (IJCSNS),2008
3. An Introduction to Universal Verification Methodology for the digital design of Integrated circuits (IC’s): A Review
4. Gigabit ethernet switches using a shared buffer architecture
5. Implementation of 10Gb Ethernet Switch Hardware Platform with a Network Processor and a 10Gb EMAC
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