CMOS two-quadrant multiplier using transistor triode regime-Reference-Cited by-同舟云学术

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CMOS two-quadrant multiplier using transistor triode regime

Published:1992-05 Issue:5 Volume:27 Page:831-833
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Filanovsky I.M.,Baltes H.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx1/4/3652/00133175.pdf?arnumber=133175

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Low Power CMOS Analog Multiplier using Regulated Cascode Current Mirror based on Translinear principle;2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT);2022-10-07

2. DTMOS Based High Bandwidth Four-Quadrant Analog Multiplier;Informacije MIDEM - Journal of Microelectronics, Electronic Components and Materials;2020-09-20

3. A new strategy to design low power translinear based CMOS analog multiplier;Integration;2019-11

4. Wide bandwidth CMOS four-quadrant mixed mode analogue multiplier using a second generation current conveyor circuit;TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES;2018-03-30

5. Squaring Circuits;Synthesis of Computational Structures for Analog Signal Processing;2011-07-26

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