Design of a Ring-Amplifier Robust Against PVT Variations in Deep-Nanoscale FinFET CMOS
Author:
Affiliation:
1. Nova School of Science and Technology,Department of Materials Science,Lisbon,Portugal
2. Nova School of Science and Technology,Department of Electrical and Computer Engineering,Lisbon,Portugal
Funder
Xilinx
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9666151/9666153/09666185.pdf?arnumber=9666185
Reference16 articles.
1. A Systematic Design Methodology for Class-AB-Style Ring Amplifiers
2. A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers
3. A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS
4. A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC
5. A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier
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