A Novel Area Efficient TIEO based Reversible Logic Gates in QCA Paradigm-Reference-Cited by-同舟云学术

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A Novel Area Efficient TIEO based Reversible Logic Gates in QCA Paradigm

Published:2023-10-11 Issue: Volume: Page:
ISSN:
Container-title:2023 7th International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC)
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Author:

Kalpana K.¹,Paulchamy B.¹,Logamurthy P.²,Suganyadevi K.³,Saranya R.⁴

Affiliation:

1. Hindusthan Institute of Technology,Department of ECE,Coimbatore,India

2. Nandha Engineering College,Department of ECE,Erode,India

3. Sri Eshwar College of Engineering,Department of ECE

4. Nehru Institute of Engineering and Technology,Department of ECE,Coimbatore,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10290135/10289705/10289706.pdf?arnumber=10289706

Reference22 articles.

1. Efficient adder circuits based on a conservative reversible logic gate. In VLSI, 2002;bruce;Proceedings Annual Symposium on IEEE Computer Society Annual Symposium on,2002

2. novel reversible multiplier architecture using reversible tsg gate;thapliyal;IEEE International Conference on Computer Systems and Applications 2006,2006

3. A Review on Reversible Logic Gates and its QCA Implementation

4. Adder and Multiplier Design in Quantum-Dot Cellular Automata

5. A Novel design of Nano scale TIEO based single layer full adder and full subractor in QCA paradigm

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