A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver

Author:

Bachtold M.,Spasojevic M.,Lage C.,Ljung P.B.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 28 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Speeding Parasitic-Extraction Stage in Layout-Change-Order Validation Cycle Through Net-Tracing and Layout Trimming;Lecture Notes in Electrical Engineering;2022

2. High-Accuracy Parasitic Extraction;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14

3. 2D capacitance extraction with direct boundary methods;Engineering Analysis with Boundary Elements;2015-09

4. Statistical Capacitance Extraction Based on Continuous-Surface Geometric Model;Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits;2014

5. Process Variation-Aware Capacitance Extraction;Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits;2014

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